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-rw-r--r--hdl/lib/shift_reg.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/hdl/lib/shift_reg.py b/hdl/lib/shift_reg.py
index 6966a77..3a217de 100644
--- a/hdl/lib/shift_reg.py
+++ b/hdl/lib/shift_reg.py
@@ -43,13 +43,13 @@ def test_shiftreg_right():
yield from step()
yield dut.load.eq(0)
yield dut.en.eq(1)
- yield Settle()
for _ in range(9):
+ yield
reg_val = yield dut.reg
assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}"
val = val >> 1
- yield from step()
+
sim(dut, proc)
def test_shiftreg_left():
@@ -63,17 +63,17 @@ def test_shiftreg_left():
yield from step()
yield dut.load.eq(0)
yield dut.en.eq(1)
- yield Settle()
for _ in range(9):
+ yield
reg_val = yield dut.reg
assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}"
val = (val << 1) & 0xff
- yield from step()
+
sim(dut, proc)
if __name__ == '__main__':
shift_reg = ShiftReg(8)
- cmd(shift_reg) \ No newline at end of file
+ cmd(shift_reg)