diff options
Diffstat (limited to 'hdl/core/machine_code.csv')
| -rw-r--r-- | hdl/core/machine_code.csv | 96 |
1 files changed, 49 insertions, 47 deletions
diff --git a/hdl/core/machine_code.csv b/hdl/core/machine_code.csv index 96e73d5..d1799aa 100644 --- a/hdl/core/machine_code.csv +++ b/hdl/core/machine_code.csv @@ -1,47 +1,49 @@ -name,type,opcode,mode,description,notes -ADD,R,1,1,RD = RS1 + RS2, -ADDC,R,2,1,RD = RS1 + RS2 + FLG[0], -SUB,R,3,1,RD = RS1 - RS2, -SUBC,R,4,1,RD = RS1 - RS2 - FLG[0], -XOR,R,5,1,RD = RS1 ^ RS2, -OR,R,6,1,RD = RS1 | RS2, -AND,R,7,1,RD = RS1 & RS2, -LSL,R,8,1,RD = RS1 << RS2 (logical), -LSR,R,9,1,RD = RS1 >> RS2 (logical), -ASR,R,10,1,RD = RS1 >> RS2, -MULL,R,11,1,RD = (RS1 * RS2) & 0xFFFFFFFF, -MULH,R,12,1,RD = (RS1 * RS2) >> 32, -MULLU,R,13,1,RD = RS1 * RS2 & 0xFFFFFFFF (unsigned), -MULHU,R,14,1,RD = (RS1 * RS2) >> 32 (unsigned), -DIV,R,15,1,RD = RS1 / RS2,not implemented yet -DIVU,R,16,1,RD = RS1 / RS2 (unsigned),not implemented yet -LDW,R,17,1,RD = MEM[RS1 + offset], -LDWR,R,18,1,RD = MEM[RS1 + RS2], -STW,R,19,1,MEM[RS1 + offset] = RS2, -LDB,R,20,1,RD = MEM[RS1 + offset] & 0xFF, -LDBR,R,21,1,RD = MEM[RS1 + RS2] & 0xFF, -STB,R,22,1,MEM[RS1 + offset] = RS2 & 0xFF, -ADDI,I,64,1,RD = RS + IMM, -ADDIC,I,65,1,RD = RS + IMM + FLG[0], -SUBI,I,66,1,RD = RS - IMM, -SUBIC,I,67,1,RD = RS - IMM - FLG[0], -XORI,I,68,1,RD = RS ^ IMM, -ORI,I,69,1,RD = RS | IMM, -ANDI,I,70,1,RD = RS & IMM, -LSLI,I,71,1,RD = RS << IMM (logical), -LSRI,I,72,1,RD = RS >> IMM (logical), -ASRI,I,73,1,RD = RS >> IMM, -MULIL,I,74,1,RD = (RS * IMM) & 0xFFFFFFFF, -MULIH,I,75,1,RD = (RS * IMM) >> 32, -MULIU,I,76,1,RD = (RS * IMM) & 0xFFFFFFFF (unsigned), -MULIUH,I,77,1,RD = (RS * IMM) >> 32 (unsigned), -DIVI,I,78,1,RD = RS / IMM,not implemented yet -DIVUI,I,79,1,RD = RS / IMM (unsigned),not implemented yet -JMP,J,128,1,op depends on machine code, -JMPI,J,129,1,op depends on machine code, -NOP,C,0,1,Do nothing -> opcode = ZERO , -CALL,C,160,1,CS0=IP; IP=CS0, -RET,C,161,1,"IP = CS0, this is implemented using jmp or call instruction", -SCALL,C,162,1,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[6]; SP=CS1; FLG[16]=0; FLG[17]=0;, -INT,C,192,0,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[IMM]; SP=CS1; FLG[16]=0; FLG[17]=0;, -IRET,C,193,0,IP=CS0; SP=CS1; FLG=CS2;,
\ No newline at end of file +name,type,opcode,mode,description,notes,valid_op,wb_en,alu_op,is_imm,jump_en,mem_wr_en,mem_rd_en,mem_rw_word +ADD,R,1,1,RD = RS1 + RS2,,1,1,0,0,0,0,0,0 +ADDC,R,2,1,RD = RS1 + RS2 + FLG[0],,1,1,1,0,0,0,0,0 +SUB,R,3,1,RD = RS1 - RS2,,1,1,2,0,0,0,0,0 +SUBC,R,4,1,RD = RS1 - RS2 - FLG[0],,1,1,3,0,0,0,0,0 +XOR,R,5,1,RD = RS1 ^ RS2,,1,1,6,0,0,0,0,0 +OR,R,6,1,RD = RS1 | RS2,,1,1,5,0,0,0,0,0 +AND,R,7,1,RD = RS1 & RS2,,1,1,4,0,0,0,0,0 +NOR,R,8,1,RD = ~(RS1 | RS2),,1,1,7,0,0,0,0,0 +LSL,R,9,1,RD = RS1 << RS2 (logical),,1,1,8,0,0,0,0,0 +LSR,R,10,1,RD = RS1 >> RS2 (logical),,1,1,9,0,0,0,0,0 +ASR,R,11,1,RD = RS1 >> RS2,,1,1,10,0,0,0,0,0 +MULL,R,12,1,RD = (RS1 * RS2) & 0xFFFFFFFF,,1,1,13,0,0,0,0,0 +MULH,R,13,1,RD = (RS1 * RS2) >> 32,,1,1,14,0,0,0,0,0 +MULLU,R,14,1,RD = RS1 * RS2 & 0xFFFFFFFF (unsigned),,1,1,11,0,0,0,0,0 +MULHU,R,15,1,RD = (RS1 * RS2) >> 32 (unsigned),,1,1,12,0,0,0,0,0 +DIV,R,16,1,RD = RS1 / RS2,not implemented yet,0,0,0,0,0,0,0,0 +DIVU,R,17,1,RD = RS1 / RS2 (unsigned),not implemented yet,0,0,0,0,0,0,0,0 +LDW,R,18,1,RD = MEM[RS1 + offset],,1,1,0,0,0,0,1,1 +LDWR,R,19,1,RD = MEM[RS1 + RS2],,1,1,0,0,0,0,1,1 +STW,R,20,1,MEM[RS1 + offset] = RS2,,1,0,0,0,0,1,0,1 +LDB,R,21,1,RD = MEM[RS1 + offset] & 0xFF,,1,1,0,0,0,0,1,0 +LDBR,R,22,1,RD = MEM[RS1 + RS2] & 0xFF,,1,1,0,0,0,0,1,0 +STB,R,23,1,MEM[RS1 + offset] = RS2 & 0xFF,,1,0,0,0,0,1,0,0 +ADDI,I,64,1,RD = RS + IMM,,1,1,0,1,0,0,0,0 +ADDIC,I,65,1,RD = RS + IMM + FLG[0],,1,1,1,1,0,0,0,0 +SUBI,I,66,1,RD = RS - IMM,,1,1,2,1,0,0,0,0 +SUBIC,I,67,1,RD = RS - IMM - FLG[0],,1,1,3,1,0,0,0,0 +XORI,I,68,1,RD = RS ^ IMM,,1,1,6,1,0,0,0,0 +ORI,I,69,1,RD = RS | IMM,,1,1,5,1,0,0,0,0 +ANDI,I,70,1,RD = RS & IMM,,1,1,4,1,0,0,0,0 +NORI,I,71,1,RD = ~(RS1 | IMM),,1,1,7,1,0,0,0,0 +LSLI,I,72,1,RD = RS << IMM (logical),,1,1,8,1,0,0,0,0 +LSRI,I,73,1,RD = RS >> IMM (logical),,1,1,9,1,0,0,0,0 +ASRI,I,74,1,RD = RS >> IMM,,1,1,10,1,0,0,0,0 +MULIL,I,75,1,RD = (RS * IMM) & 0xFFFFFFFF,,1,1,13,1,0,0,0,0 +MULIH,I,76,1,RD = (RS * IMM) >> 32,,1,1,14,1,0,0,0,0 +MULIUL,I,77,1,RD = (RS * IMM) & 0xFFFFFFFF (unsigned),,1,1,11,1,0,0,0,0 +MULIUH,I,78,1,RD = (RS * IMM) >> 32 (unsigned),,1,1,12,1,0,0,0,0 +DIVI,I,79,1,RD = RS / IMM,not implemented yet,0,0,0,1,0,0,0,0 +DIVUI,I,80,1,RD = RS / IMM (unsigned),not implemented yet,0,0,0,1,0,0,0,0 +JMP,J,128,1,op depends on machine code,,1,0,0,0,1,0,0,0 +JMPI,J,129,1,op depends on machine code,,1,0,0,1,1,0,0,0 +NOP,C,0,1,Do nothing -> opcode = ZERO ,,1,0,0,0,0,0,0,0 +CALL,C,160,1,CS0=IP; IP=CS0,,1,0,0,0,0,0,0,0 +RET,C,161,1,"IP = CS0, this is implemented using jmp or call instruction",,1,0,0,0,0,0,0,0 +SCALL,C,162,1,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[6]; SP=CS1; FLG[16]=0; FLG[17]=0;,,1,0,0,0,0,0,0,0 +INT,C,192,0,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[IMM]; SP=CS1; FLG[16]=0; FLG[17]=0;,,1,0,0,0,0,0,0,0 +IRET,C,193,0,IP=CS0; SP=CS1; FLG=CS2;,,1,0,0,0,0,0,0,0 |