1 files changed, 30 insertions, 0 deletions
diff --git a/archive/testing/up_counter_tb.py b/archive/testing/up_counter_tb.py
new file mode 100644
index 0000000..7c2e8d2
--- /dev/null
+++ b/archive/testing/up_counter_tb.py
@@ -0,0 +1,30 @@
+from amaranth.sim import Simulator
+from up_counter import UpCounter
+
+dut = UpCounter(25)
+
+
+def bench():
+    # Disabled counter should not overflow.
+    yield dut.en.eq(0)
+    for _ in range(30):
+        yield
+        assert not (yield dut.ovf)
+
+    # Once enabled, the counter should overflow in 25 cycles.
+    yield dut.en.eq(1)
+    for _ in range(25):
+        yield
+        assert not (yield dut.ovf)
+    yield
+    assert (yield dut.ovf)
+
+    # The overflow should clear in one cycle.
+    yield
+    assert not (yield dut.ovf)
+
+sim = Simulator(dut)
+sim.add_clock(1e-6) # 1 MHz
+sim.add_sync_process(bench)
+with sim.write_vcd("up_counter.vcd"):
+    sim.run()
+\ No newline at end of file