diff options
| -rw-r--r-- | hdl/core.py | 157 |
1 files changed, 147 insertions, 10 deletions
diff --git a/hdl/core.py b/hdl/core.py index 506de96..9355bf3 100644 --- a/hdl/core.py +++ b/hdl/core.py @@ -1,6 +1,7 @@ +from ast import Del from curses.ascii import SI from multiprocessing import dummy -from tkinter import S +from tkinter import S, Y from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique @@ -9,7 +10,7 @@ from utils import cmd class Reg(Elaboratable): - def __init__(self): + def __init__(self, sim=False): # sim is only for modularity, does nothing for this # enable write self.wr_en = Signal(1) @@ -49,7 +50,8 @@ class Reg(Elaboratable): # internal signals self._user_mode = Signal(1) - self._sp_write = Signal(1) + self._sp_inc_dec = Signal(1) + self._wr_alu_flg = Signal(1) self.zx = Signal(32) #0 self.ax = Signal(32) #1 @@ -110,26 +112,39 @@ class Reg(Elaboratable): m.d.sync += self.sp.eq(self.cs1) m.d.sync += self.flg.eq(self.cs2) - m.d.comb += self._sp_write.eq(0) + m.d.comb += self._sp_inc_dec.eq(0) + m.d.comb += self._wr_alu_flg.eq(1) # writeback setup with m.If(self.wr_en): with m.Switch(self.rd_addr): with m.Case(self.zx.idx): # do not write to zero register pass + with m.Case(self.ip.idx): #do not directly write to ip register pass + with m.Case(self.flg.idx): # mask top half of register to prevent writing to flags in user mode - m.d.sync += self.flg.eq(self.rd & Cat(Const(0xFFFF, 16), Repl(~self._user_mode, 16))) + with m.If(~self._user_mode): + m.d.sync += self.flg.eq(self.rd) # system mode, full control + with m.Else(): + m.d.sync += self.flg.eq(Cat(self.rd[:16], self.flg[16:])) # usermode can only effect lower 16 bits + + # don't update flags from alu + m.d.comb += self._wr_alu_flg.eq(0) + with m.Case(self.sp.idx): - m.d.comb += self._sp_write.eq(1) + m.d.comb += self._sp_inc_dec.eq(1) m.d.sync += self.sp.eq(self.rd) + with m.Case(): - m.d.sync += self.flg.eq(Cat(self.alu_flgs, self.flg[len(self.alu_flgs):])) # update flags if register is not being written to m.d.sync += self.reg_arr[self.rd_addr].eq(self.rd) - with m.If(~self._sp_write & self.stack_instr): + with m.If(self._wr_alu_flg): + m.d.sync += self.flg.eq(Cat(self.alu_flgs, self.flg[len(self.alu_flgs):])) # update flags if register is not being written to + + with m.If(~self._sp_inc_dec & self.stack_instr): with m.If(self.stack_down_up): m.d.sync += self.sp.eq(self.sp - 1) with m.Else(): @@ -151,6 +166,128 @@ class Reg(Elaboratable): return m +def test_reg(filename="reg.vcd"): + dut = Reg(sim=True) + + def init(): + for i in range(16): + yield dut.reg_arr[i].eq(i) + yield Settle() + + def step(): + yield Settle() # settle comb logic before clock + yield # clock edge + yield Settle() # settle comb logic after clock + yield Delay(5e-7) # used for debugging, change values on neg edge of clock + + def proc1(): + yield from init() + + # test combinational output + for i in range(16): + yield dut.rs1_addr.eq(i) + yield Settle() + assert (yield dut.rs1) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}' + for i in range(16): + yield dut.rs2_addr.eq(i) + yield Settle() + assert (yield dut.rs2) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}' + + # test writeback with writeback disabled + yield from init() + for i in range(16): + yield dut.rd_addr.eq(i) + yield dut.rd.eq(i + 1) + yield from step() + if (i != dut.ip.idx) and (i != dut.flg.idx): # flag gets update by the alu + assert (yield dut.reg_arr[i]) == i, f'ERROR writing to {dut.reg_arr[i].name} != {i}' + + # test writeback with writeback enabled + for i in range(16): + yield from init() + yield dut.wr_en.eq(1) + yield dut.rd_addr.eq(i) + yield dut.rd.eq(i - 1) + yield from step() + if (i != dut.zx.idx) and (i != dut.ip.idx): + assert (yield dut.reg_arr[i]) == i-1, f'ERROR writing to {dut.reg_arr[i].name} != {i-1}' + elif i == dut.zx.idx: + assert (yield dut.zx) == 0, f'ERROR {dut.zx.name} != 0' + elif i == dut.ip.idx: + # ip should be incremented and not written to + assert (yield dut.reg_arr[i]) == i+1, f'ERROR {dut.ip.name} != {i + 1} should not be able to be directly written to' + + yield dut.wr_en.eq(0) + + # test flag register security + yield dut.flg.eq(0) + yield dut.flg.user_mode.eq(1) + yield dut.flg[15].eq(1) + yield dut.flg[31].eq(1) + yield dut.rs1_addr.eq(dut.flg.idx) + yield Settle() + assert (yield dut.rs1) == 0x00008000, f'ERROR: able to read upper 16 bits of flg reg in user mode' + + # test flag register security + yield dut.flg.eq(0) + yield dut.wr_en.eq(1) + yield dut.flg.user_mode.eq(1) + yield dut.flg[15].eq(1) + yield dut.flg[31].eq(1) + yield dut.rd_addr.eq(dut.flg.idx) + yield dut.rd.eq(0xABCD5789) + yield from step() + assert (yield dut.flg) == (0x80020000 | 0x5789), f'ERROR: able to write to upper 16 bits of flg reg in user mode' + + yield dut.flg.eq(0) + yield dut.flg.user_mode.eq(0) + yield dut.flg[15].eq(1) + yield dut.flg[31].eq(1) + yield dut.rs1_addr.eq(dut.flg.idx) + yield Settle() + assert (yield dut.rs1) == 0x80008000, f'ERROR: able to read all bits of flg reg in system mode' + + yield dut.flg.eq(0) + yield dut.wr_en.eq(1) + yield dut.flg.user_mode.eq(0) + yield dut.flg[15].eq(1) + yield dut.flg[31].eq(1) + yield dut.rd_addr.eq(dut.flg.idx) + yield dut.rd.eq(0xABCD5789) + yield from step() + assert (yield dut.flg) == (0xABCD5789), f'ERROR: unamble to write to all bits in supervisor mode' + + # make sure not to write alu flags when directly writing to flg register + yield dut.flg.eq(0) + yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width)) + yield dut.wr_en.eq(1) + yield dut.flg.user_mode.eq(0) + yield dut.flg[15].eq(1) + yield dut.flg[31].eq(1) + yield dut.rd_addr.eq(dut.flg.idx) + yield dut.rd.eq(0xFFFF0000) + yield from step() + assert (yield dut.flg) == (0xFFFF0000), f'ERROR: alu status should not be to flag' + + # check to make sure alu is writing values + yield dut.flg.eq(0) + yield dut.alu_flgs.eq(Repl(1, dut.alu_flgs.width)) + yield dut.wr_en.eq(1) + yield dut.flg.user_mode.eq(0) + yield dut.rd_addr.eq(dut.zx.idx) # can be anything except flg register + yield dut.rd.eq(0xFFFF0000) # this does not matter + yield from step() + assert (yield dut.flg) == (0x0000001f ), f'ERROR: alu is not writing to flg register' + + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(filename): + sim.run() + + # class ASAP32Core(Elaboratable): # def __init__(self): @@ -292,7 +429,7 @@ class ALU(Elaboratable): m.d.comb += self.c_out.eq(self.tmp[32]) m.d.comb += self.overflow.eq(self.tmp[32] ^ self.tmp[31]) m.d.comb += self.out.eq(self.tmp[0:32]) - m.d.comb += self.neg.eq(self.out.as_signed() < 0) + m.d.comb += self.neg.eq(self.out[31]) m.d.comb += self.zero.eq(self.out == 0) m.d.comb += self.odd.eq(self.out[0]) @@ -427,7 +564,7 @@ def test_alu(filename="alu.vcd"): if __name__ == '__main__': reg = Reg() - cmd(reg, None) + cmd(reg, test_reg) # hdl = ALU() # cmd(hdl, test_alu) |