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-rw-r--r--hdl/template.py.txt49
1 files changed, 29 insertions, 20 deletions
diff --git a/hdl/template.py.txt b/hdl/template.py.txt
index 64f0655..cc6bdac 100644
--- a/hdl/template.py.txt
+++ b/hdl/template.py.txt
@@ -1,36 +1,45 @@
from amaranth import *
from amaranth.sim import Simulator, Settle, Delay
+from enum import Enum, unique
-from utils import cmd
+from hdl.utils import cmd, step, sim
+from hdl.lib.in_out_buff import InOutBuff # used for timing analysis
-class Template(Elaboratable):
- def __init__(self):
- ...
- self.ports = [...]
+class HDL(Elaboratable):
+ def __init__(self, **kargs):
+ ...
- def elaborate(self, platform):
- m = Module()
+ ports_in = []
+ ports_out = []
+ self.ports = {'in': ports_in, 'out': ports_out}
- ...
+ self.sim = kargs["sim"] if "sim" in kargs else False
- return m
+ def elaborate(self, platform=None):
+ m = Module()
-def test(filename="out.vcd"):
- dut = ...
+ # dummy sync for simulation only needed if there is no other sequential logic
+ if self.sim == True:
+ dummy = Signal()
+ m.d.sync += dummy.eq(~dummy)
- def proc1():
...
+
+ return m
- sim = Simulator(dut)
- sim.add_clock(1e-6)
- sim.add_sync_process(proc1)
-
- with sim.write_vcd(filename):
- sim.run()
+# test addition
+def test_hdl():
+ dut = HDL(sim=True)
+ def proc():
+ yield from step #step clock
+ yield Settle() #needed if for combinatorial logic
+ yield dut.something #read value
+ sim(dut, proc)
+
if __name__ == '__main__':
- shift_reg = Template(...)
- cmd(shift_reg, test) \ No newline at end of file
+ hdl = InOutBuff(HDL())
+ cmd(hdl)