diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | hdl/core/jump_ctl.py | 2 | ||||
| -rw-r--r-- | hdl/core/reg.py | 2 |
3 files changed, 5 insertions, 7 deletions
@@ -8,23 +8,21 @@ GEN_VCD := $(HDL_FOLDER)/gen_vcd HDL := $(wildcard $(HDL_FOLDER)/**/*.py) -all: test +all: test-nw sim: $(HDL) echo 'Deprecated, FU' # cude but simple, and works... cc: $(HDL) - export PYTHONPATH=$(PYTHONPATH) for file in $(HDL); do \ - python3 $$file cc; \ + export PYTHONPATH=$(PYTHONPATH); python3 $$file cc; \ done # cude but simple, and works... v: - export PYTHONPATH=$(PYTHONPATH) for file in $(HDL); do \ - python3 $$file v; \ + export PYTHONPATH=$(PYTHONPATH); python3 $$file v; \ done test: diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py index 468c2e3..94dd8f2 100644 --- a/hdl/core/jump_ctl.py +++ b/hdl/core/jump_ctl.py @@ -21,7 +21,7 @@ class JumpCtl(Elaboratable): def __init__(self, **kargs): self.alu_flags = Signal(len(ALUFlags), reset_less=True) - self.op = Signal(3, reset_less=True) + self.op = Signal(e2s(JumpOpCodes), reset_less=True) self.signed_bits = Signal(2, reset_less=True) self.cond_true = Signal(reset_less=True) # true if jump condition is met diff --git a/hdl/core/reg.py b/hdl/core/reg.py index 3526408..130de94 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -89,7 +89,7 @@ class Reg(Elaboratable): self.reg_arr = Array(reg_list) - ports_in = [self.wr_en, self.alu_flgs, self.int_sig, self.iret, self.call, self.jump, self.rd_addr, self.rd, self.rs1_addr, self.rs2_addr] + ports_in = [self.wr_en, self.alu_flgs, self.int_sig, self.iret, self.call, self.jump, self.rd_addr, self.stall, self.rd, self.rs1_addr, self.rs2_addr] ports_out = [self.int_en, self.user_mode, self.rs1, self.rs2, self.ip] self.ports = {'in': ports_in, 'out': ports_out} |