added rtlil export

1 files changed, 6 insertions, 1 deletions

diff --git a/hdl/utils.py b/hdl/utils.py
index 792e8a7..9c0277d 100644
--- a/hdl/utils.py
+++ b/hdl/utils.py
@@ -9,7 +9,7 @@ import random
 #hdl specific imports
 from amaranth import *
 from amaranth import Elaboratable
-from amaranth.back import verilog, cxxrtl
+from amaranth.back import verilog, cxxrtl, rtlil
 from amaranth.sim import Settle, Delay, Simulator
 
 #custom imports 
@@ -46,6 +46,11 @@ def cmd(hdl):
         with open(os.path.join(CXXRTL_DIR, os.path.basename(sys.argv[0]).replace('.py', '.cc')), 'w') as f:
             f.write(out)
 
+    elif sys.argv[1] == "rt":
+        out = rtlil.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out'])
+        with open(os.path.join(RTLIL_DIR, os.path.basename(sys.argv[0]).replace('.py', '.il')), 'w') as f:
+            f.write(out)
+
 def e2s(e: Enum):
     '''
     Get signal length from enum, returns ceil(log2(len(e))))