diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-06-23 23:04:28 -0500 |
---|---|---|
committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-23 23:04:28 -0500 |
commit | 382b73b0989dc00093f4e5daa67d4386722b19fb (patch) | |
tree | 472203a26f5a4b0e573c1528633f90d019d9f2a3 /hdl/testing/inc.v | |
parent | 26169bec7ae7b85d938f5d3c6e969885f2230541 (diff) |
basic myhdl setup working
Diffstat (limited to 'hdl/testing/inc.v')
-rw-r--r-- | hdl/testing/inc.v | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/hdl/testing/inc.v b/hdl/testing/inc.v deleted file mode 100644 index 2f3291b..0000000 --- a/hdl/testing/inc.v +++ /dev/null @@ -1,39 +0,0 @@ -// File: inc.v -// Generated by MyHDL 0.11 -// Date: Sun Jun 19 22:02:52 2022 - - -`timescale 1ns/10ps - -module inc ( - count, - enable, - clock, - reset -); -// Incrementer with enable. -// -// count -- output -// enable -- control input, increment when 1 -// clock -- clock input -// reset -- asynchronous reset input - -output [7:0] count; -reg [7:0] count; -input enable; -input clock; -input reset; - - -always @(posedge clock, negedge reset) begin: INC_SEQ - if (reset == 0) begin - count <= 0; - end - else begin - if (enable) begin - count <= (count + 1); - end - end -end - -endmodule |