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authorjjsuperpower <jjs29356@gmail.com>2022-06-19 22:20:25 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-06-19 22:20:25 -0500
commit26169bec7ae7b85d938f5d3c6e969885f2230541 (patch)
tree86752721345fc913acc1d3f8f9e4fdd322c97ae9 /hdl/testing/inc.v
added hdl folder
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diff --git a/hdl/testing/inc.v b/hdl/testing/inc.v
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+// File: inc.v
+// Generated by MyHDL 0.11
+// Date: Sun Jun 19 22:02:52 2022
+
+
+`timescale 1ns/10ps
+
+module inc (
+ count,
+ enable,
+ clock,
+ reset
+);
+// Incrementer with enable.
+//
+// count -- output
+// enable -- control input, increment when 1
+// clock -- clock input
+// reset -- asynchronous reset input
+
+output [7:0] count;
+reg [7:0] count;
+input enable;
+input clock;
+input reset;
+
+
+always @(posedge clock, negedge reset) begin: INC_SEQ
+ if (reset == 0) begin
+ count <= 0;
+ end
+ else begin
+ if (enable) begin
+ count <= (count + 1);
+ end
+ end
+end
+
+endmodule