diff options
author | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
---|---|---|
committer | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
commit | 63626f2f6fc7e8912a349f120e37998cd1a05554 (patch) | |
tree | a4a10c448613bd683b79a2f5dbef892edef0d49d /hdl/testing/async_reset.py | |
parent | 762e8b8786d8c921726c8ddc92a2513f42dad683 (diff) |
moveing file around
Diffstat (limited to 'hdl/testing/async_reset.py')
-rw-r--r-- | hdl/testing/async_reset.py | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py deleted file mode 100644 index 4760df7..0000000 --- a/hdl/testing/async_reset.py +++ /dev/null @@ -1,21 +0,0 @@ -from amaranth import * -from amaranth.cli import main - - -class ClockDivisor(Elaboratable): - def __init__(self, factor): - self.v = Signal(factor) - self.o = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return m - - -if __name__ == "__main__": - m = Module() - m.domains.sync = sync = ClockDomain("sync", async_reset=True) - m.submodules.ctr = ctr = ClockDivisor(factor=16) - main(m, ports=[ctr.o, sync.clk])
\ No newline at end of file |