basic alu coded and tested

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+# Vertex KISS 32 - Machine Code Spec
+^ So Vertex is already a name for an FPGA, should we change this?
+I propose a different name:
+
+    ASAP Soc 32 a KISS inspired architecture
+
+    As
+    Simple
+    As
+    Possible
+
+## General Instruction Format
+    X = HEX
+    B = BIN
+
+    d = HEX (not used /  don't care)
+
+    MAX INSTRUCTIIONS = 256
+    ALL INSTRUCTIONS ARE ATOMIC
+
+    ALL MEMORY ADDRESSES ARE 32-bit, not 8-bit
+    ^ What do you think about this? 32 bits is usually and 'int' in C
+    This would extend the address space, kinda
+
+    Also I have been reading about caching, I think the instruction width needs to be the same as the data memory
+
+### C-Type, Control
+    XX       X    X       XXXX
+    Opcode   d    RS1     IMM
+
+### I-Type, Immediate
+    XX        X     X     XXXX
+    Opcode    RD    RS1   IMM
+
+### R-Type, Arithmetic
+    XX         X      X      X      XXX
+    Opcode     RD     RS1    RS2    ddd
+
+### JR-Type, Compare and Jump
+    XX          X                   X      X        XXX
+    Opcode      Jump Condition      RS1    RS2      ddd
+
+### JI-Type, Compare and Jump
+    XX          X                X     XXXX            
+    Opcode      Jump Condition   RS1   IMM
+
+## Registers
+    Maximum registers = 16
+    Register width = 32
+    All are R/W except 0X
+
+    0X      Always Zero
+    AX      GP-0
+    BX      GP-1
+    CX      GP-2
+    DX      GP-3
+    EX      GP-4
+    FX      GP-5
+    GX      GP-6
+    HX      GP-7
+    HI      Mult/Div Hi
+    LO      Mult/Div Lo
+    FG      Processor Flags
+    CR      Control register (Writable only in supervisor mode)
+    IP      Instruction Pointer
+    SP      Stack Pointer
+    JA      Jump Address
+
+    ^ I have added this, it is part of my proposal for changing how jumps work
+
+
+### FG Flag Register Bitfield
+    These registers are Read/Write
+    They are automaticaly writen two by the processor
+
+    FG[0]           Carry
+    FG[1]           Overflow
+    FG[2]           Zero
+    FG[3]           Sign
+    FG[4-31]        RESERVED
+
+### CR Control Register Bitfield
+    These register are Read/Write in System mode, Read Only in User Mode
+
+    CR[0]           Interupt Enable
+    CR[1]           User Mode
+    CR[2]           DMA
+    CR[2-31]        RESERVED
+
+
+
+## Integer Instructions
+
+### R-Type
+    ADD     RD, RS1, RS2        RD = RS1 + RS2
+    SUB     RD, RS1, RS2        RD = RS1 - RS2
+    XOR     RD, RS1, RS2        RD = RS1 ^ RS2
+    OR      RD, RS1, RS2        RD = RS1 | RS2
+    AND     RD, RS1, RS2        RD = RS1 & RS2
+    LSL     RD, RS1, RS2        RD = RS1 << RS2 (logical)
+    LSR     RD, RS1, RS2        RD = RS1 >> RS2 (logical)
+    ASR     RD, RS1, RS2        RD = RS1 >> RS2
+    MUL     RD, RS1, RS2     HI,LO = RS1 * RS2
+    MULU    RD, RS1, RS2     HI,LO = RS1 * RS2
+    DIV     RD, RS1, RS2     HI,LO = RS1 / RS2
+    DIVU    RD, RS1, RS2     HI,LO = RS1 / RS2 (unsigned)
+
+    #LDB     RD, RS1, RS2        RD = &(RS1 + RS2)           Load Byte
+    #STB     RD, RS1, RS2        &(RS1 + RS2) = (RD >> 24)   Store Byte
+    LDW     RD, RS1, RS2        RD = &(RS1 + RS2)           Load Word (4 bytes)
+    STW     RD, RS1, RS2        &(RS1 + RS2) = RD           Store Word (4 bytes)
+
+    # Depricated?
+
+
+### I-Type
+    ADDI    RD, RS, IMM         RD = RS + IMM
+    SUBI    RD, RS, IMM         RD = RS - IMM
+    XORI    RD, RS, IMM         RD = RS ^ IMM
+    ORI     RD, RS, IMM         RD = RS | IMM
+    ANDI    RD, RS, IMM         RD = RS & IMM
+    LSLI    RD, RS, IMM         RD = RS << IMM (logical)
+    LSRI    RD, RS, IMM         RD = RS >> IMM (logical)
+    ASRI    RD, RS, IMM         RD = RS >> IMM
+    MULI    dd, RS, IMM      HI,LO = RS * IMM
+    MULIU   dd, RS, IMM      HI,LO = RS * IMM
+    DIVI    dd, RS, IMM      HI,LO = RS / IMM
+    DIVIU   dd, RS, IMM      HI,LO = RS / IMM (unsigned)
+
+    #LDBI    RD, RS, RS2     RD = &(RS + IMM)           Load Byte
+    #STBI    RD, RS, RS2     &(RS + IMM) = (RD >> 24)   Store Byte
+    LDWI    RD, RS, RS2     RD = &(RS + IMM)           Load Word (4 bytes)
+    STWI    RD, RS, RS2     &(RS + IMM) = RD           Store Word (4 bytes)
+
+    # Depricated?
+
+
+### JR Instructions
+    Compare and then jump (IP = JMP)
+
+    JMP     0          if (True)
+    JMP     1          if (RS1 != RS2)
+    JMP     2          if (RS1 == RS2)
+    JMP     3          if (RS1 >  RS2)  Unsigned
+    JMP     4          if (RS1 >= RS2)  Unsigned
+
+    JMP     C          if (RS1 >  RS2)  Signed
+    JMP     D          if (RS1 >= RS2)  Signed
+
+### JI Instructions
+    Compare and then jump (IP = JMP)
+
+    JMPI     0          if (True)
+    JMPI     1          if (RS1 != IMM)
+    JMPI     2          if (RS1 == IMM)
+    JMPI     3          if (RS1 >  IMM)  Unsigned
+    JMPI     4          if (RS1 >= IMM)  Unsigned
+
+    JMPI     C          if (RS1 >  IMM)  Signed
+    JMPI     D          if (RS1 >= IMM)  Signed
+
+### Jump Aliases
+
+    JEQ
+    JLT     
+    JGT
+    JLE
+    JGE
+    JLTU 
+    JGTU
+    JLEU   
+    JGEU   
+
+
+### Control Instructions
+    NOP                     Do nothing -> opcode = ZERO
+    PUSHR   RS              SP+=1     ;*SP = RS
+    POPR    RS              RS = *SP  ;SP-=1
+    PUSHA                   PUSHR AX, BX, CX, DX, EX, FX, GX, FX, HI, LO, FG, CR, IP, SP, JA
+    POPA                    POP reverse PUSHR, SP not affected
+    PUSHI   IMM             SP+=1     ;*SP = IMM
+    INVP    IMM             Invalidate entry in TLB
+    RET                     POPR IP;
+    CALL                    PUSHR IP; IP = JMP;
+    INT                     PUSHA ;IP = IDT[IMM]
+    IRET                    POPR FLG; POPR SP; POPR IP
+    SIF                     Set interrupt flag
+    CIF                     Clear interrupt flag
+
+## Interrupt Descriptor Table
+This will be in a fixed memory location, this will contain pointers to the interupt function. Once an interupt is entered, all interupts are turned off.
+
+    IDT[0]          Divide-by-zero exception
+    IDT[1]          Hardware error (NMI)
+    IDT[2]          Overflow
+    IDT[3]          Invalid Opcode
+    IDT[4]          General-protection fault
+    IDT[5]          TLB miss
+    IDT[6]          Software interrupt (reserved for OS)
+    IDT[7-31]       Platform interrupts (PIC, hard drive, keyboard, etc.)
+
+    IDTMSK[0-31]    Interupt mask, when interupt is entered the mask bit for the coorisponding interupt will be disabled.
+                    The software is responsible for renabling the mask bit
+
+You get 32 :)
+Also, I was think of making the OS handle TLP misses
+
+
+
+
+
+## Page Directory
+
+The page directory contains 1024 page tables that have 1024 entries.
+
+^ Stupid question: Do we need a page directory? Also I have a very limited size for cache, idt, tlb, etc. Plan on having around 100 Kbits
+
+### Page table layout
+
+    PT[0]           Present
+    PT[1]           R/W
+    PT[2]           User-mode
+    PT[3-4]         RESERVED
+    PT[5]           Accessed
+    PT[6-7]         RESERVED
+    PT[8-31]        Physical address of page table (XX * 2^16 + XXXX)
+
+        *This is still WIP but I wanted to get your input on the layout. I also have
+        the jank memory offset that will more than likely change.*