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| author | jjsuperpower <jjs29356@gmail.com> | 2022-08-15 16:17:40 -0500 |
|---|---|---|
| committer | jjsuperpower <jjs29356@gmail.com> | 2022-08-15 16:17:40 -0500 |
| commit | c27ad0c92e710e14b7d6d50839936ceda51dd017 (patch) | |
| tree | a6732fee7bc9dd29d7a05d54b6e80abc16d59b62 /doc | |
| parent | 6c02607b0972976da182c2e7b318dd6f9c5baf20 (diff) | |
updated ISA
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/DJ-ISA_rev_0.0.5.md (renamed from doc/DJ-ISA_rev_0.0.4.md) | 39 |
1 files changed, 23 insertions, 16 deletions
diff --git a/doc/DJ-ISA_rev_0.0.4.md b/doc/DJ-ISA_rev_0.0.5.md index 8c7266d..66f57a6 100644 --- a/doc/DJ-ISA_rev_0.0.4.md +++ b/doc/DJ-ISA_rev_0.0.5.md @@ -25,12 +25,12 @@ I propose a different name: Also I have been reading about caching, I think the instruction width needs to be the same as the data memory ### C-Type, Control - XX X XXXXX - Opcode RS1 IMM + XX X X XXXX + Opcode d RS1 IMM ### I-Type, Immediate XX X X XXXX - Opcode RD RS IMM + Opcode RD RS1 IMM ### R-Type, Arithmetic XX X X X XXX @@ -60,27 +60,34 @@ I propose a different name: FX GP-7 HI Mult/Div Hi LO Mult/Div Lo - FLG Processor Flags - CRX Control register (Writable only in supervisor mode) + FG Processor Flags + CR Control register (Writable only in supervisor mode) IP Instruction Pointer SP Stack Pointer - JMP Jump Address + JA Jump Address ^ I have added this, it is part of my proposal for changing how jumps work -### FLG Register Bitfield +### FG Flag Register Bitfield These registers are Read/Write + They are automaticaly writen two by the processor + + FG[0] Carry + FG[1] Overflow + FG[2] Zero + FG[3] Sign + FG[4-31] RESERVED + +### CR Control Register Bitfield + These register are Read/Write in System mode, Read Only in User Mode + + CR[0] Interupt Enable + CR[1] User Mode + CR[2] DMA + CR[2-31] RESERVED - FLG[0] Carry - FLG[1] Overflow - FLG[2] Zero - FLG[3] Sign - FLG[4]* Interrupt Enable - FLG[5]* User Mode - FLG[6-31] RESERVED -*To be moved to control register* ## Integer Instructions @@ -169,7 +176,7 @@ I propose a different name: NOP Do nothing -> opcode = ZERO PUSHR RS SP+=1 ;*SP = RS POPR RS RS = *SP ;SP-=1 - PUSHA PUSHR AX, BX, CX, DX, EX, FX, GX, FX, HI, LO, FLG, CRX, IP, SP, JMP + PUSHA PUSHR AX, BX, CX, DX, EX, FX, GX, FX, HI, LO, FG, CR, IP, SP, JA POPA POP reverse PUSHR, SP not affected PUSHI IMM SP+=1 ;*SP = IMM INVP IMM Invalidate entry in TLB |