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author | jjsuperpower <jjs29356@gmail.com> | 2022-06-19 22:20:25 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-06-19 22:20:25 -0500 |
commit | 26169bec7ae7b85d938f5d3c6e969885f2230541 (patch) | |
tree | 86752721345fc913acc1d3f8f9e4fdd322c97ae9 /doc/src/01-About.md |
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diff --git a/doc/src/01-About.md b/doc/src/01-About.md new file mode 100644 index 0000000..0468708 --- /dev/null +++ b/doc/src/01-About.md @@ -0,0 +1,73 @@ +# About this Manual + +This manual describes the architecture and programming environment of a Vertex +Mark I microprocessor. This manual applies to application programmers, operating +system programmers and BIOS designers. + +## Notational Conventions + +This manual uses specific notation for data-structure formats, for symbolic +representation and for hexadecimal and binary numbers. A review of this notation +makes the manual easier to read. + +### Bit and Byte Order + +In illustrations of data structures in memory, smaller addresses appear toward +the bottom of the figure; addresses increase toward the top. Bit positions are +numbered from right to left. The numerical value of a set bit is two raised to +the power of the bit position. Vertex processors are "little endian" machines; +this means the bytes of a word are numbered starting from the least significant +byte. Figure 1.1 illustrates these conventions. + +### Reserved Bits + +In many register and memory layout descriptions, certain bits are marked as +**reserved**. When bits are marked as reserved, it is essential for +compatibility with future processors that software treat these bits as having +a future, but unknown, use. These bits should be treated as, not only undefined, +but unpredictable. + +### Instruction Operands + +When instructions are represented symbolically, a subset of the Vertex-32 +assembly language is used. In this subset, an instruction has the following +format: + +``` +label: mnemonic argument1, argument2, argument3 +``` + +where: + +* A **label** is an identifier which is followed by a colon +* A **mnemonic** is a reserved name for an instruction opcode +* The operands *argument1*, *argument2* and *argument3* are optional. There may + be from zero to three operands, depending on the opcode. + +When three operands are present in an arithmetic or logical operation, the first +operand is the destination register and the remaining two are either source +registers or immediate values. For example: + +``` +load: ADDI AX, BX, subtotal +``` + +In this example, `ADDI` is the mnemonic identifier of an opcode, `AX` is the +destination operand, and `BX` and `subtotal` are the source operands. + +### Hexadecimal and Binary Numbers + +Base 16 (hexadecimal) numbers are represented by a '0x' followed by a string of +hexadecimal digits. A hexadecimal digit is a character from '0' to '9' and 'A' +to 'F'. Base 2 (binary) numbers are represented by a string of 1s and 0s, +sometimes preceded by '0b' (for example, 0b1010). The '0b' designation is only +used in situations in which confusion about a number's base may arise. + +### Exceptions + +An exception is an event that typically occurs when an instruction causes an +error. For example, an attempt to divide by zero generates a divide-by-zero +exception. All exceptions provide either an error code or 0, indicating no +error. An error code reports additional information about the error. For +example, a page fault would provide a fault code indicating what caused the page +fault. |