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author | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
commit | 63626f2f6fc7e8912a349f120e37998cd1a05554 (patch) | |
tree | a4a10c448613bd683b79a2f5dbef892edef0d49d /deprecated/hdl_lab/template.py | |
parent | 762e8b8786d8c921726c8ddc92a2513f42dad683 (diff) |
moveing file around
Diffstat (limited to 'deprecated/hdl_lab/template.py')
-rw-r--r-- | deprecated/hdl_lab/template.py | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/deprecated/hdl_lab/template.py b/deprecated/hdl_lab/template.py deleted file mode 100644 index 77eb18c..0000000 --- a/deprecated/hdl_lab/template.py +++ /dev/null @@ -1,69 +0,0 @@ -from typing import Callable -from myhdl import * -from myhdl_wrap import Myhdl_Wrapper - -import random -from random import randint - -random.seed(63) - -class Template(Myhdl_Wrapper): - def __init__(self): - super().__init__() - - # Main code, this is the actual logic - @staticmethod - @block - def Template(args): # this must be the same name as the class name - - @instance - def logic(): - while True: - ... - - return logic - - - @block - def tb(self, func: Callable): - reset = Signal(False) - clk = Signal(False) - ... - - dut = func(..., clk=clk, reset=reset) - - @always(delay(...)) - def clock_gen(): - clk.next = not clk - - @instance - def monitor(): - while True: - ... - - @instance - def stimulus(): - ... - - raise StopSimulation - - - return dut, clock_gen, monitor, stimulus - - def export(self): - reset = Signal(False) - clk = Signal(False) - ... - - # assigning signals, kargs only - self._export(..., clk=clk, reset=reset) - - -def test_template_sim(): - hdl = Template() - hdl.sim() - -def test_template_cosim(): - hdl = Template() - hdl.export() - hdl.cosim() |